> Multidisciplinary Hardware Engineer specializing in FPGA systems, Embedded development, RTL design, and Linux-based hardware integration.
> Hello! I am a passionate Multidisciplinary Hardware Engineer with a profound interest in bridging the gap between low-level hardware and high-level software.
> My journey started with programming microcontrollers and rapidly evolved into designing custom hardware architectures using Verilog/VHDL, developing on FPGA boards, and integrating Linux-based systems.
> I specialize in RTL Design, Embedded Systems, Communication Protocols, and Hardware-Software integration. I enjoy the challenge of building efficient, robust, and high-performance electronic systems from the silicon level up to the operating system.
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Architected a custom 5-stage pipelined RISC-V RV32I processor using Verilog HDL. The architecture integrates a hazard detection unit, data forwarding multiplexers to resolve read-after-write (RAW) dependencies, and static branch prediction. The design was rigorously simulated and verified in ModelSim before FPGA synthesis, demonstrating high instruction throughput and cycle efficiency.
Engineered a low-latency Linux character device driver to interface with a custom PCIe-based FPGA hardware accelerator. The implementation utilizes Direct Memory Access (DMA) for high-bandwidth data transfers, bypassing the CPU to reduce overhead. It includes robust interrupt request (IRQ) handling and kernel-space memory mapping for user-space application interaction.
Developed an end-to-end embedded IoT system centered around an ESP32 microcontroller with custom-designed PCB routing. The firmware leverages FreeRTOS for preemptive multi-threading, prioritizing real-time sensor data acquisition over I2C and SPI buses. Data is serialized and transmitted securely over MQTT, utilizing AES encryption to ensure payload integrity across the network.
Designed a highly optimized Universal Asynchronous Receiver-Transmitter (UART) intellectual property (IP) core in SystemVerilog. The module features parameterized baud rate generation and deeply buffered FIFOs for resilient asynchronous communication. The RTL was validated against corner cases using the Universal Verification Methodology (UVM) and synthesized via Xilinx Vivado.
I am currently looking for new opportunities in Multidisciplinary Hardware Engineering, FPGA design, and Embedded Systems. Whether you have a question, a project proposal, or just want to discuss hardware architecture, my inbox is open.